Title :
A 1.5 GHz robust SRAM array optimized for cell area
Author :
Kharouf, Saeed ; Chatila, Lama ; Mansour, Mohammad ; Chehab, Ali
Author_Institution :
Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Beirut, Lebanon
Abstract :
A low power SRAM macro is designed in 90nm TSMC model technology. The design is customized with Cadence Environment for minimal bit cell area, resulting in an area of 0.370 mm2. To reduce leakage power in standby mode, the SRAM architecture employs a dynamic supply voltage management scheme. The 64 kbits sub-array can run at 1.54 GHz at 1.0V supply voltage. Results demonstrated that the macro has a 6% failure probability when tested for threshold voltage process variation.
Keywords :
SRAM chips; integrated circuit design; low-power electronics; SRAM architecture; TSMC model technology; cadence environment; cell area; dynamic supply voltage management scheme; failure probability; frequency 1.5 GHz; leakage power reduction; low power SRAM macro; robust SRAM array; size 90 nm; standby mode; threshold voltage process variation; voltage 1 V; Arrays; Logic gates; Random access memory; Switches; SRAM Architecture; low power; process variation; sleep transistor; static random access memory (SRAM);
Conference_Titel :
Microelectronics (ICM), 2010 International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-61284-149-6
DOI :
10.1109/ICM.2010.5696166
