True correlated double sampling and comparator design for time-based image sensors

This paper presents a time-domain correlated double sampling (CDS) method for time-based/PWM image sensors. The concept has been realized in the pixel circuit design for a spiking asynchronous, time-based image sensor (ATIS). The pixel circuitry includes a two-stage voltage comparator with tunable hysteresis and dynamic current control, and pixel-level state logic. The sensor, based on a 240times304 pixel array, was implemented in a standard 0.18 mum CMOS process. We present measurements from the fabricated chip and compare them to results from theoretical considerations. Implications of the proposed CDS method on the comparator design in terms of chip area and power consumption are discussed and quantified.