Partnership for a rapid yield enhancement solution in a manufacturing environment on a 0.65 μm triple level metal device

A speed related problem degraded the yield of a 0.65 μm triple level metal device. Reducing the channel length was the most simple and cost effective approach to improve device speed. However, an overly aggressive downsized channel length could also cause device leakage. To determine the optimal channel length with adequate speed performance and without leakage, a series of experiments were run to establish a yield model as a function of channel length and device threshold voltage (Vt). The Vt was varied by adjusting the channel implant dose. Instead of using masks with different sizings, the channel length was varied by adjusting photo exposure time and lightly doped drain (LDD) implant dose. This approach greatly reduced the cost of experiments and shortened the learning cycle. A strong correlation was established by Analysis of Variances (ANOVA) between yield and p-channel transistor length. The range of operational channel length was defined, where higher channel length caused poor speed performance and lower channel length caused device leakage. An interim process with increased photo exposure time was implemented immediately to ensure die shipment quantity and delivery schedule. In parallel, the optimal mask sizing was determined and this mask regenerated such that the original photo exposure when used with this mask would re-center the process. The interim process was then eliminated to streamline manufacturability. The optimized process resulted in significant yield improvement. Strong partnerships were established among device engineering, process engineering, and manufacturing groups to achieve yield enhancement in a timely manner without compromising manufacturability and customer deliveries