DocumentCode
2256692
Title
Decimal Floating Point for future processors
Author
Fahmy, Hossam A H ; ElDeeb, Tarek ; Hassan, Mahmoud Yousef ; Farouk, Yasmin ; Eissa, Ramy Raafat
Author_Institution
Electron. & Commun. Dept., Cairo Univ., Cairo, Egypt
fYear
2010
fDate
19-22 Dec. 2010
Firstpage
443
Lastpage
446
Abstract
Many new designs for Decimal Floating Point (DFP) hardware units have been proposed in the last few years. To date, only the IBM POWER6 and POWER7 processors include internal units for decimal floating point processing. We have designed and tested several DFP units including an adder, multiplier, divider, square root, and fused-multiply-add compliant with the IEEE 754-2008 standard. This paper presents the results of using our units as part of a vector co-processor and the anticipated gains once the units are moved on chip with the main processor.
Keywords
floating point arithmetic; microprocessor chips; IBM POWER6 processor; IBM POWER7 processor; IEEE 754-2008 standard; adder; decimal floating point hardware unit; decimal floating point processing; divider; fused-multiply-add compliant; multiplier; square root; vector co-processor; Adders; Benchmark testing; Computers; Encoding; Hardware; Program processors;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics (ICM), 2010 International Conference on
Conference_Location
Cairo
Print_ISBN
978-1-61284-149-6
Type
conf
DOI
10.1109/ICM.2010.5696183
Filename
5696183
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