A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment

Author

Weng, Ro-Min ; Lu, Yun-Chih ; Liu, Chun-Yu

Author_Institution

Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan

fYear

2009

fDate

24-27 May 2009

Firstpage

1301

Lastpage

1304

Abstract

An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.05 GHz. The locking time of AIPWCL is less than 40 ns within the operation frequency band. The power dissipation is 4.38 mW at 1.2 V voltage supply. The peak-to-peak jitter is less than 1 ps at an input clock frequency of 1 GHz while adjusting various duty cycles.

Keywords

CMOS integrated circuits; UHF integrated circuits; adaptive control; clocks; delay lock loops; phase locked loops; timing jitter; AIPWCL; arbitrary-input pulsewidth control loop; clock signals; delay-locked loop; duty cycle adjustment; duty cycle corrector; frequency 770 MHz to 1.05 GHz; input clock frequency; locking time; operation frequency; peak-to-peak jitter; power 4.38 mW; power dissipation; time 40 ns; tsmc CMOS process; voltage 1.2 V; Charge pumps; Circuits; Clocks; Delay; Frequency; Jitter; Partial discharges; Signal generators; Space vector pulse width modulation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on

Conference_Location

Taipei

Print_ISBN

978-1-4244-3827-3

Electronic_ISBN

978-1-4244-3828-0

Type

conf

DOI

10.1109/ISCAS.2009.5118002

Filename

5118002