Multi-objective Network-on-Chip synthesis with transaction level simulation

The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple design objectives rather than one single objective subset, so that designers can make flexible decisions according to different design objectives and budgets. The switch area model is obtained from RTL implementation and system performances are measured using SystemC TLM simulation. Experiments on multimedia and general benchmark applications demonstrate the efficiency of this method.