A case study of design optimization through variable width selection

A large number of system-on-a-chip (SoC) designs utilize fixed-point computation units due to their simplicity and efficiency over floating-point functional units. The selection of variable widths for fixed-point computing is critical in determining the computation accuracy and hardware complexity of these SoCs. In this paper, we present an optimization procedure for a wireless receiver. Extensive analysis is performed in selecting the widths of all fixed-point variables to minimize the circuit size and power without degrading the wireless transmission bit-error-rate (BER) significantly. Designed using a 0.18 mum standard cell library, the final receiver has a core of 16.5 mm² and delivers a maximal throughput of 5 Mbps in simulation with 557 mW power dissipation. The judicious selection of variable widths leads to 17% and 9% decrease in area and power dissipation with only 0.1 dB degradation in BER.