Design of a robust, high performance standard cell threshold logic family for DSM technology

This paper presents the threshold logic latch (TLL), which provides a high performance, low power alternative to traditional CMOS logic networks. TLL is highly robust, even in deep sub-micron technology nodes. Experimental results obtained from simulation of a commercial 65 nm low power process demonstrate a static noise margin up to an order of magnitude greater than those of existing implementations of threshold logic. Examples of automated synthesis of pipelined multipliers using a combination of standard CMOS and a small number of TLL gates are shown through simulation to improve both area and total power by a factor of up to 1.5 and reduce leakage power by a factor of up to 2.3.