Physical design aware selection of energy-efficient and low-energy nanometer flip-flops

Author

Alioto, Massimo ; Consoli, Elio ; Palumbo, Gaetano

Author_Institution

Dept. of Inf. Eng., Univ. of Siena, Siena, Italy

fYear

2010

fDate

19-22 Dec. 2010

Firstpage

60

Lastpage

63

Abstract

In this paper, a comparison of the most representative flip-flop (FF) topologies in a 65-nm CMOS technology is carried out. For the first time in the literature, local wires capacitances are included in the transistor-level design loop, allowing to reach the actual optimum designs, given the huge impact that local interconnects have on both energy and delay (E-D) of FFs. The investigation permits to identify the most suitable FFs for low-energy and energy-efficient circuits in nanometer technologies.

Keywords

CMOS digital integrated circuits; flip-flops; network topology; CMOS technology; energy and delay; energy-efficient circuits; flip-flop topologies; local wires capacitances; low-energy nanometer flip-flops; physical design aware selection; size 65 nm; transistor-level design loop; Clocks; Energy efficiency; Flip-flops; Latches; Layout; Topology; Wires; Clocking; Energy-Delay; Energy-Efficiency; Flip-Flops; Interconnects; Layout Impact; Low-Power; VLSI;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics (ICM), 2010 International Conference on

Conference_Location

Cairo

Print_ISBN

978-1-61284-149-6

Type

conf

DOI

10.1109/ICM.2010.5696206

Filename

5696206