Efficient hardware implementation of a new pseudo-random bit sequence generator

In this paper we propose a new linear congruential generator (LCG) based pseudo random bit-sequence generator (PRBG) and its hardware implementation. Linear congruential generators (LCGs) of the form x_i+1 = ax_i + b(mod m), have been used to generate pseudorandom numbers. However these generators have been known to be insecure. The proposed PRBG couples four such LCGs and is secure. A preliminary proof of security is outlined in this paper. The PRBG generates bit-sequences that pass all NIST pseudo randomness tests. Our PRBG has a very efficient hardware implementation because the modulo operation is with respect to 2ⁿ as opposed to p times q in the blum-blum-shub (BBS) generator, where p and q are large prime numbers. We also show that the hardware implementation can be easily pipelined, thereby increasing the throughput in spite of the hardware having large word-length inputs (n ges 128). A 4-stage pipelined hardware was implemented in VHDL for n = 128 and the synthesized hardware was simulated. Simulation results showed a 2.81 fold increase in throughput (number of pseudo-random bits output per unit time) compared to the non-pipelined version.