Convolutional Vector Symbol Decoder Phase II on FPGA: correct with second choice

The concept of vector symbol decoding (VSD) for convolutional codes was shown to be a good decoding technique for convolutional codes with large nonbinary symbols or packet-symbols. However, the hardware implementation in Phase I was designed for very simple error patterns, which can be decoded using only one syndrome vector. This new Phase II decoder extends its ability to decode more complicated error patterns using up to four syndrome vectors. For Phase II, the decoding was done by using the concept of correct with second choice only. Lab prototype was implemented on an FPGA board and worked exactly as expected. The next phase will be VSD decoder without the help of second choices.