Resource constrained VLSI architecture for implantable neural data compression systems

Neural recordings from high-density microelectrode arrays implanted in the cortex require time-frequency domain processing to alleviate the data telemetry bottlenecks of bandwidth and power. Our previous work has shown that the energy compaction capability of the discrete wavelet transform (DWT) offers a practical data compression solution that faithfully preserves the information in the neural signals. This paper presents a complete compression system including both lossy and lossless compression schemes, namely the DWT and run length encoding. Performance tradeoffs and key design decisions for implantable applications are analyzed. A 32-channel, 4-level version of the circuit is presented. Custom designed in 0.5 mum CMOS, occupying only 5.75 mm² and consuming 3mW of power (95 muW per channel at 25Ks/sec), the implantable compression circuit is well suited for intra-cortical neural interface applications.