Surge current minimization in high-level synthesis

Power gating is the most effective technique to reduce the leakage power of an idle functional unit. However, when the functional unit is turned on, a sudden discharge, called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In this paper, we point out the high-level synthesis (including operation scheduling and functional unit binding) has a great impact on the maximum surge current. Then, based on that observation, we propose an integer linear program (ILP) to formally draw up the surge current minimization problem in the high-level synthesis stage. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.