DocumentCode
2257833
Title
GoldMine: Automatic assertion generation using data mining and static analysis
Author
Vasudevan, Shobha ; Sheridan, David ; Patel, Sanjay ; Tcheng, David ; Tuohy, Bill ; Johnson, Daniel
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Illinois at Urbana Champaign, Champaign, IL, USA
fYear
2010
fDate
8-12 March 2010
Firstpage
626
Lastpage
629
Abstract
We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. We present results of using GoldMine for assertion generation of the RTL of a 1000-core processor design that is still in an evolving stage. Our results show that GoldMine can generate complex, high coverage assertions in RTL, thereby minimizing human effort in this process.
Keywords
data mining; digital circuits; logic design; program diagnostics; 1000 core processor design; GoldMine; automatic assertion generation; data mining; register transfer level design; static analysis; Data engineering; Data mining; Formal verification; Hardware; Humans; Logic; Process design; Registers; Space technology; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4244-7054-9
Type
conf
DOI
10.1109/DATE.2010.5457129
Filename
5457129
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