DocumentCode
2258032
Title
Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph
Author
Wang Huan ; Zhang Yang ; Mei Chen ; Ling Ming
Author_Institution
Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., Nanjing, China
fYear
2010
fDate
8-12 March 2010
Firstpage
598
Lastpage
601
Abstract
Energy consumption has always been considered as the key issue of the state-of-the-art SoCs. Implementing an on-chip Cache is one of the most promising solutions. However, traditional Cache may suffer from performance and energy penalties due to the Cache conflict. In order to deal with this problem, this paper firstly introduces a Time-Slotted Cache Conflict Graph to model the behavior of Data Cache conflict. Then, we implement an Integer Nonlinear Programming to select the most profitable data pages and employ Virtual Memory System to remap those data pages, which can cause severe Cache conflict within a time slot, to the on-chip Scratchpad Memory (SPM). In order to minimize the swapping overhead of dynamic SPM allocation, we introduce a novel SPM controller with a tightly coupled DMA to issue the swapping operations without CPU´s intervention. The proposed method can optimize all of the data segments, including global data, heap and stack data in general, and reduce 24.83% energy consumption on average without any performance degradation.
Keywords
cache storage; embedded systems; graph theory; integer programming; nonlinear programming; power aware computing; system-on-chip; virtual storage; SPM controller; SoC; coupled DMA; data cache conflict; embedded system; energy consumption; energy-oriented dynamic SPM allocation; integer nonlinear programming; on-chip cache; on-chip scratchpad memory; time-slotted cache conflict graph; virtual memory system; Embedded system; Energy consumption; Indium phosphide; Memory management; Nonlinear dynamical systems; Programming profession; Runtime; Scanning probe microscopy; System performance; Voice mail; Energy Optimization; Scratchpad Memory; Time-Slotted Cache Conflict Graph; Virtual Memory System;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4244-7054-9
Type
conf
DOI
10.1109/DATE.2010.5457138
Filename
5457138
Link To Document