DocumentCode
2258043
Title
A theoretical discussion on performance limits of CMOS charge pumps
Author
Cabrini, A. ; Gobbi, L. ; Torelli, G.
Author_Institution
Dept. of Electron., Pavia Univ, Italy
Volume
2
fYear
2005
fDate
28 Aug.-2 Sept. 2005
Abstract
This paper presents a study of the theoretical performance of CMOS integrated charge pumps (CPs). The discussion is based on a behavioural model of the CP and a mathematical manipulation of power efficiency definition. The CP theoretical limit is found in terms of both power efficiency and maximum driving capability. The basic idea is to analyze the performance of any CP only considering the voltage gain, the output resistance, the number of capacitors and parasitic capacitances. Experimental results are presented to validate the theoretical analysis.
Keywords
CMOS integrated circuits; driver circuits; integrated circuit modelling; network analysis; power electronics; CMOS integrated charge pumps; CP theoretical limit; maximum driving capability; output resistance; parasitic capacitance; power efficiency definition; voltage gain; Capacitors; Charge pumps; Energy consumption; Mathematical model; Performance analysis; Power supplies; Semiconductor device modeling; Switches; Topology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN
0-7803-9066-0
Type
conf
DOI
10.1109/ECCTD.2005.1522986
Filename
1522986
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