Title :
A quasi-delay-insensitive dual-rail adder working in subthreshold region
Author :
Chang, Xiaofei ; Lian, Yong
Author_Institution :
Electr. & Comput. Eng. Dept., Nat. Univ. of Singapore, Singapore, Singapore
Abstract :
In this paper, we propose a novel design of quasi-delay-insensitive dual-rail asynchronous adder working at subthreshold region using 0.13 mum standard CMOS technologies. Power Delay Product (PDP) as measure of merit is used for comparison with other recent published subthreshold adders. Low-power consumption, low PDP and high robustness are demonstrated.
Keywords :
CMOS logic circuits; adders; asynchronous circuits; asynchronous adder; low-power consumption; power delay product; quasi-delay-insensitive dual-rail adder; size 0.13 mum; standard CMOS technology; subthreshold region; Adders; CMOS technology; Delay; Design engineering; Power engineering and energy; Power engineering computing; Protocols; Robustness; Voltage; Wires;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118069
