Title :
Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs
Author :
Adeniran, Olujide A. ; Demosthenous, Andreas
Author_Institution :
Dept. of Electron. & Electr. Eng., London Univ. Coll., UK
fDate :
28 Aug.-2 Sept. 2005
Abstract :
This paper attempts to theoretically determine the optimal number of bit-per-stage required for the CMOS low-voltage (Vsupply < 2.5Vth) radix-2 pipeline ADC architecture, with minimization of power dissipation and analog complexity as the overall goal. The design of a 1.5 V, 21 mW, 25 MS/s, 10-bit pipeline ADC is employed as reference. The results of the optimization analysis show that 2.5 bit-per-stage is the optimum for the 10-bit ADC design with digital error correction. This can also be generalized for any n-bit low-voltage pipeline ADC.
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit complexity; circuit optimisation; integrated circuit design; low-power electronics; 1.5 V; 10 bit; 21 mW; CMOS radix-2 pipeline ADC architecture; analog complexity; bit-per-stage optimization; digital error correction; low-power CMOS pipeline ADC; low-voltage CMOS pipeline ADC; optimization analysis; power dissipation minimization; Design optimization; Educational institutions; Energy consumption; Error correction; High power amplifiers; Low voltage; Minimization; Pipelines; Power dissipation; Sampling methods;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1522991
