Title :
An area and power efficient discrete-time chaos generator circuit
Author :
Dudek, P. ; Juncu, V.D.
Author_Institution :
Sch. of Electr. & Electron. Eng., Manchester Univ., UK
fDate :
28 Aug.-2 Sept. 2005
Abstract :
A discrete-time chaos generator circuit suitable for low power applications is presented in this paper. The generator is based on a three-transistor circuit which creates an easily adjustable chaos map characteristic. The circuit has a very compact implementation which makes it suitable for applications where many random noise generators are required on the same chip. The operation of the circuit has been verified via simulations in a 0.6μm CMOS process.
Keywords :
CMOS analogue integrated circuits; chaos generators; discrete time systems; low-power electronics; nonlinear network synthesis; transistor circuits; 0.6 micron; CMOS process; chaos map characteristic; discrete-time chaos generator circuit; low power electronics; random noise generator; three-transistor circuit; Buffer storage; CMOS technology; Chaos; Nonlinear circuits; Power generation; Signal generators; Silicon; Switches; Switching circuits; Voltage;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1522999
