DocumentCode
2258333
Title
High performance partially depleted SOI using spike RTA
Author
Kang, Laegu ; Grudowski, Paul ; Dhandapani, Veer ; Jeon, Yongjoo ; Goktepeli, Sinan ; Min, Byoung ; Yeap, Geofiey ; Foisy, Mark ; Anderson, Steven ; Mendicino, Michael ; Venkatesan, Suresh
Author_Institution
Semicond. Products Sector, Motorola Inc., Austin, TX, USA
fYear
2003
fDate
29 Sept.-2 Oct. 2003
Firstpage
37
Lastpage
38
Abstract
Thinner Si body (700 Å) SOI CMOS was successfully demonstrated with spike RTA on 0.13 μm technology with 45 nm gate lengths and 16Å gate oxide. Spike RTA exhibited excellent short channel effect and lower miller capacitance (Cmiller), resulting in faster circuit speed and lower dynamic power compared to the conventional RTA. Spike RTA also showed comparable floating body effects and stress induced current degradation.
Keywords
CMOS integrated circuits; MOSFET; rapid thermal annealing; silicon-on-insulator; 0.13 micron; 100 Å; 16 Å; 45 nm; Si-SiO2; circuit speed; dynamic power; floating body effects; miller capacitance; partially depleted SOI; short channel effect; spike RTA; stress induced current degradation; thinner Si body SOI CMOS; CMOS integrated circuits; MOSFETs; Rapid thermal annealing; Silicon on insulator technology;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2003. IEEE International
ISSN
1078-621X
Print_ISBN
0-7803-7815-6
Type
conf
DOI
10.1109/SOI.2003.1242888
Filename
1242888
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