Enhanced 32-bit Microprocessor-based SoC for Energy Efficient MP3 Decoding in Portable Devices

Author

Lin, Yi-Ting ; Huang, Ing-Jer

Author_Institution

Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung

fYear

2007

fDate

10-14 Jan. 2007

Firstpage

1

Lastpage

2

Abstract

This paper presents a 32-bit microprocessor-based SoC optimized for low power MP3 decoding in portable devices. The SoC consists of a 32-bit ARM-like microprocessor core with an instruction set extension and two optional hardware accelerators for IMDCT and poly-phase synthesis modules. Depending on the configuration, the enhancements allow the SoC to run at lower frequency (78%~86%) and reduce energy consumption by 25.4%~38.5% in decoding MP3 streams.

Keywords

audio coding; decoding; discrete cosine transforms; instruction sets; reduced instruction set computing; speech processing; system-on-chip; ARM-like microprocessor core; IMDCT; energy efficient MP3 decoding; hardware accelerators; instruction set extension; microprocessor-based SoC; poly-phase synthesis modules; portable devices; Acceleration; Application software; Costs; Decoding; Digital audio players; Energy efficiency; Filters; Hardware; ISO standards; Microprocessors;

fLanguage

English

Publisher

ieee

Conference_Titel

Consumer Electronics, 2007. ICCE 2007. Digest of Technical Papers. International Conference on

Conference_Location

Las Vegas, NV

Print_ISBN

1-4244-0763-X

Electronic_ISBN

1-4244-0763-X

Type

conf

DOI

10.1109/ICCE.2007.341572

Filename

4146209