Device physics considerations for SOI domino circuit design

The ongoing need to increase the speed in tandem with decrease in power consumption has necessitated for an alternative viable technology. Due to device physics and structural properties (i.e., reduced junction capacitance, higher driving current etc) and limited technology transfer, Partially-Depleted (PD) SOI technology has become the de-facto candidate for replacing Bulk CMOS technology. It has matured to an extent that it can now be implemented in most of the applications. This paper explains how design parameters for pseudo n-MOS can be changed to maximize the advantage of SOI technology. Further, we extend this idea to dynamic logic circuits and evaluate its viability