Title :
Device physics considerations for SOI domino circuit design
Author :
Subba, Niraj ; Mitra, Souvick ; Salman, Akram ; Ioannou, Dimitris E.
Author_Institution :
Dept. of Electr. & Comput. Eng., George Mason Univ., Fairfax, VA, USA
Abstract :
The ongoing need to increase the speed in tandem with decrease in power consumption has necessitated for an alternative viable technology. Due to device physics and structural properties (i.e., reduced junction capacitance, higher driving current etc) and limited technology transfer, Partially-Depleted (PD) SOI technology has become the de-facto candidate for replacing Bulk CMOS technology. It has matured to an extent that it can now be implemented in most of the applications. This paper explains how design parameters for pseudo n-MOS can be changed to maximize the advantage of SOI technology. Further, we extend this idea to dynamic logic circuits and evaluate its viability
Keywords :
MOS logic circuits; logic design; silicon-on-insulator; SOI domino circuit design; dynamic logic circuit; partially depleted SOI technology; pseudo n-MOS; CMOS logic circuits; CMOS technology; Capacitance; Circuit synthesis; Driver circuits; Energy consumption; Frequency; Logic circuits; MOS devices; Physics;
Conference_Titel :
Semiconductor Device Research Symposium, 2001 International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-7432-0
DOI :
10.1109/ISDRS.2001.984546
