DocumentCode
2258864
Title
Noise considerations and detailed comparison of low standby gate/sub-threshold leakage digital circuits in nano-scale SOI technology
Author
Das, K. Krishna ; Joshi, Rajiv V. ; Chuang, Ching-Te Kent ; Brown, Richard B.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear
2003
fDate
29 Sept.-2 Oct. 2003
Firstpage
87
Lastpage
88
Abstract
In this paper, we present a comparison of 4 low leakage techniques from noise considerations, and discusses their suitability for currently used PD-SOI and future FD-SOI devices.
Keywords
CMOS digital integrated circuits; integrated circuit modelling; integrated circuit noise; nanotechnology; silicon-on-insulator; PD-SOI devices; low standby gate; nanoscale SOI technology; noise considerations; subthreshold leakage digital circuits; CMOS digital integrated circuits; Integrated circuit modeling; Integrated circuit noise; Nanotechnology; Silicon on insulator technology;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2003. IEEE International
ISSN
1078-621X
Print_ISBN
0-7803-7815-6
Type
conf
DOI
10.1109/SOI.2003.1242910
Filename
1242910
Link To Document