• DocumentCode
    2258931
  • Title

    Design and implementation of the high speed TCP/IP Offload Engine

  • Author

    Chung, Shen-Ming ; Li, Chun-Yi ; Lee, Hsiao-Hui ; Li, Jeng-Han ; Tsai, Yau-Cheng ; Chen, Chi-Chun

  • Author_Institution
    Home Networking Technol. Center Ind. Technol. Res. Inst., Tainan
  • fYear
    2007
  • fDate
    17-19 Oct. 2007
  • Firstpage
    574
  • Lastpage
    579
  • Abstract
    As the growth of Ethernet speed surpassed the growth of microprocessor performance, TCP/IP Offload Engine (TOE) technology has emerged and aimed at not only releasing servers and communication systems from burdened conventional TCP/IP stack but improving the network utilization rate. To lower the risk in developing TOE, one may rely on certain platform containing a single or plurality of embedded microprocessor(s). However, one may find that it is not easy to use such slow-clocked microprocessor(s) to achieve the high speed goal. Hence this paper proposed 5 design guidelines and a corresponding architecture in TOE offloading which come out with experimental results showing that the proposed design further approaches the limit of 1Gbps Ethernet, i.e. 858.82 Mbps as receiving and 793.25 Mbps as transmitting while saves 2/3 to 3/4 computation power compared with using conventional TCP/IP stack.
  • Keywords
    embedded systems; field programmable gate arrays; local area networks; logic design; microprocessor chips; transport protocols; Ethernet; FPGA; computer architecture; embedded microprocessor; firmware; high speed TCP/IP offload engine; logic design; network utilization rate; Engines; Information technology; TCPIP;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Communications and Information Technologies, 2007. ISCIT '07. International Symposium on
  • Conference_Location
    Sydney,. NSW
  • Print_ISBN
    978-1-4244-0976-1
  • Electronic_ISBN
    978-1-4244-0977-8
  • Type

    conf

  • DOI
    10.1109/ISCIT.2007.4392084
  • Filename
    4392084