New process and pixel structure of an SOI-CMOS imager

We present architecture, process design and results from test pixels of a new Active Pixel Sensor (APS) imager implemented in 0.8 μm SOI-CMOS technology. The conventional partially-depleted SOI-CMOS process has been altered by adding one lithography for buried oxide window opening and two implants into the handle wafer. Results on front illuminated photodiode arrays show that the Quantum Efficiency (QE) are 2-10x improved in peak and red spectral response, respectively, compared to bulk APS imagers. Dark current tests on photodiodes and pixels indicate a periphery-dominated and voltage-dependent leakage current of 5-20 nA/cm² at 3V. Pixel linearity error of ∼4% is observed at 80% of saturation. Test results indicate directions for further reduction of the dark current.