Study for CMOS device characteristics affected by ultra thin wafer thinning

Wafer thinning and fabrication of through-Si via (TSV) and micro-bump are key processes in 3D LSI. Because of mechanical stress under these processes, electrical deviations of CMOS devices such as DRAM are occurred. And the other hand, the thinner Si chip becomes, the more risky impurity ion contamination attacks the Si device. We will report about the result of DRAM retention time reduced to one third by Cu contamination whose thickness is less than 50μm. And also report about the example for investigation of several gettering methods.