Title :
Dickson charge pump circuit design with parasitic resistance in power lines
Author_Institution :
Japan Flash Design Center, Micron Japan, Ltd., Tokyo, Japan
Abstract :
Parasitic resistance in power and ground lines is considered for Dickson charge pump circuit designs, and its equivalent model is modified for low voltage IC designs. When the optimization is done for maximized output current or for minimized rise time, it is not necessary to increase the number of stages, but it is necessary to increase the pumping capacitors. The impact of the parasitic resistance in addition to the parasitic capacitance on charge pump circuit performances is discussed. The analytical results are compared with the SPICE simulation and the model has a sufficient accuracy within a typical error of 10%.
Keywords :
power cables; power integrated circuits; pumps; underground cables; Dickson charge pump circuit design; low voltage IC designs; parasitic capacitance; parasitic resistance; power lines; pumping capacitors; Analytical models; Capacitors; Charge pumps; Circuit synthesis; Clocks; Integrated circuit modeling; Low voltage; Optimized production technology; Parasitic capacitance; SPICE;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118117
