• DocumentCode
    2259111
  • Title

    Power-balanced asynchronous logic

  • Author

    Murphy, Julian ; Yakovlev, Alex

  • Author_Institution
    Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
  • Volume
    2
  • fYear
    2005
  • fDate
    28 Aug.-2 Sept. 2005
  • Abstract
    The susceptibility of cryptographic devices to power analysis has proved to be a significant security risk, and is becoming increasingly mainstream stemming from the make-up of all devices - CMOS logic. This paper proposes using asynchronous logic, enhanced to be power-balanced, to design devices resistant to power analysis.
  • Keywords
    CMOS logic circuits; asynchronous circuits; asynchronous sequential logic; cryptography; CMOS logic; asynchronous logic; cryptographic device; power analysis; security risk; CMOS logic circuits; Clocks; Cryptography; Energy consumption; Logic devices; Power measurement; Semiconductor device modeling; Signal analysis; Synchronization; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
  • Print_ISBN
    0-7803-9066-0
  • Type

    conf

  • DOI
    10.1109/ECCTD.2005.1523031
  • Filename
    1523031
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2259111