Title :
Power-balanced asynchronous logic
Author :
Murphy, Julian ; Yakovlev, Alex
Author_Institution :
Sch. of Electr., Electron. & Comput. Eng., Newcastle upon Tyne Univ., UK
fDate :
28 Aug.-2 Sept. 2005
Abstract :
The susceptibility of cryptographic devices to power analysis has proved to be a significant security risk, and is becoming increasingly mainstream stemming from the make-up of all devices - CMOS logic. This paper proposes using asynchronous logic, enhanced to be power-balanced, to design devices resistant to power analysis.
Keywords :
CMOS logic circuits; asynchronous circuits; asynchronous sequential logic; cryptography; CMOS logic; asynchronous logic; cryptographic device; power analysis; security risk; CMOS logic circuits; Clocks; Cryptography; Energy consumption; Logic devices; Power measurement; Semiconductor device modeling; Signal analysis; Synchronization; Timing;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1523031
