Title :
Three-dimensional integration scheme using hybrid wafer bonding and via-last TSV process
Author :
Takeda, Kenji ; Aoki, Masaki ; Hozawa, K. ; Furuta, F. ; Yanagisawa, A. ; Kikuchi, Hiroaki ; Mitsuhashi, Takaharu ; Kobayashi, Hideo
Author_Institution :
Assoc. of Super-Adv. Electron. Technol. (ASET), Hachioji, Japan
Abstract :
A wafer-level three-dimensional (3D) integration scheme for forming via-last through-silicon vias (TSVs) was developed. This scheme includes wafer-to-wafer (W2W) stacking technology with a copper/polymer hybrid bonding and a via-last TSV process compatible with a copper/low-k interconnect structure. Bonding of a copper/polymer hybrid wafer with a ventilation channel structure provides good copper-to-copper bonding as well as good polymer-to-polymer bonding without producing any large bonding voids. Via-last TSVs (8 μm in diameter and 25 μm in length) were successfully formed in the bonded wafer, indicating the effectiveness of the proposed 3D integration scheme.
Keywords :
integrated circuit interconnections; three-dimensional integrated circuits; wafer bonding; 3D integration scheme; W2W stacking technology; copper-low-k interconnect structure; copper-polymer hybrid bonding; copper-polymer hybrid wafer; copper-to-copper bonding; hybrid wafer bonding; polymer-to-polymer bonding; three-dimensional integration scheme; ventilation channel structure; via-last TSV process; via-last through-silicon vias; wafer-level 3D integration scheme; wafer-level three-dimensional integration scheme; wafer-to-wafer with stacking technology;
Conference_Titel :
CPMT Symposium Japan, 2012 2nd IEEE
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-2654-4
DOI :
10.1109/ICSJ.2012.6523456
