• DocumentCode
    2259330
  • Title

    Design for variability in CMOS logic circuits: Uncommitted motif arrays (UMAs)

  • Author

    Caldwell, Sonia H Paluchowski ; Cumming, David R S

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow, UK
  • fYear
    2009
  • fDate
    24-27 May 2009
  • Firstpage
    1807
  • Lastpage
    1810
  • Abstract
    Systematic and statistical variability in digital design is becoming increasingly important, and this will be even more pronounced in sub-45 nm technologies. We propose the use of uncommitted arrays of digital sub-blocks, motifs, as the basic building block for CMOS logic. These uncommitted motif arrays maximize functional flexibility, minimize routing complexity, and increase tolerance to systematic variability. The analytical selection of motifs is presented along with a design of a proposed array. We show prototypical design based on the proposed methodology to illustrate the improved regularity of designs, and the resulting routing efficiency compared to traditional uncommitted logic arrays.
  • Keywords
    CMOS logic circuits; circuit complexity; logic arrays; logic design; statistical analysis; CMOS logic circuits; UMA; digital design methodology; digital sub-blocks; routing complexity minimization; size 45 nm; statistical variability; systematic variability tolerance; uncommitted motif array design; CMOS logic circuits; CMOS technology; Integrated circuit interconnections; Logic arrays; Logic design; Logic devices; Prototypes; Resource description framework; Routing; Software libraries;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
  • Conference_Location
    Taipei
  • Print_ISBN
    978-1-4244-3827-3
  • Electronic_ISBN
    978-1-4244-3828-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.2009.5118128
  • Filename
    5118128