Mixed-mode investigation of hybrid SiC/Si cascode configurations

Author

Mihaila, A. ; Udrea, F. ; Sheng, K. ; Azar, R.

Author_Institution

Dept. of Eng., Cambridge Univ., UK

fYear

2001

fDate

2001

Firstpage

575

Lastpage

578

Abstract

The mixed-mode behaviour of a hybrid SiC/Si cascode configuration is investigated. The cascode circuit consists of a high voltage SIC JFET in series with a low power Si device, either a trench MOSFET or a SOI LDMOSFET. The two cascode modules transient characteristics are compared, and it is found that the trench-cascode is faster, but the SOI equivalent offers lower energy losses. Similar results are obtained for high temperatures (T=525 K). The SOI configuration however offers the advantage of integration of drive and protection circuitry within the same chip and can run at high temperatures without the loss of MOS gate control of the CMOS circuits

Keywords

MOSFET; elemental semiconductors; junction gate field effect transistors; semiconductor device models; silicon; silicon compounds; silicon-on-insulator; wide band gap semiconductors; 525 K; CMOS circuits; MOS gate control; SOI LDMOSFET; Si; SiC; cascode circuit; energy loss; high voltage SIC JFET; hybrid SiC/Si cascode configuration; low power Si device; mixed-mode behaviour; protection circuitry; transient characteristics; trench MOSFET; Frequency; JFET circuits; MOSFET circuits; Power MOSFET; Power engineering and energy; Protection; Silicon carbide; Temperature; Voltage; Wide band gap semiconductors;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2001 International

Conference_Location

Washington, DC

Print_ISBN

0-7803-7432-0

Type

conf

DOI

10.1109/ISDRS.2001.984583

Filename

984583