Optical solder bumps: a modular approach to monolithic optoelectronic integration

The monolithic integration of compound semiconductor devices with silicon CMOS ICs is complicated by two major factors: the large thermal expansion coefficient mismatch between silicon and other semiconductors, and the large mismatch in wafer diameters between silicon and other semiconductors. Hence, most integration of compound semiconductors and silicon is done a chip at a time using long-established hybrid bump-bonding techniques. While these methods are able to begin to satisfy many immediate application needs, they do not enjoy the economic advantages of wafer-scale, batch processing found in true monolithic integration, nor to they offer the advantages of reduced parasitics, robustness of structure and density of integration that can be obtained from monolithic integration. This paper will present a philosophy for doing monolithic heterogeneous integration called the optical solder bump concept which strives to achieve all of the economic, structural and performance advantages of true monolithic integration and to do so in a modular fashion building upon commercial silicon integrated circuit processes