Analysis of CDR with simplified selection of sampling domain

The paper deals with a statistical simulation model for a newly proposed feed-forward blind oversampling Clock and Data Recovery circuit with low hardware complexity. Unlike previous published solutions, where the selected sampling phase is constant on a fixed-length window, the new circuit selects the phase upon the occurrence of several consecutive edges in one sampling domain, i.e. the window length changes randomly. The proposed simulation model is based on periodic Markov chain representation of the domain-selection process. The averaged Bit-Error Rate can be simply computed from the steady-state of the chain. Computational complexity is determined by the jitter period length. The model includes random jitter, sinusoidal jitter, and frequency offset of transmit and receive clocks.