DocumentCode
2259593
Title
Memory testing with a RISC microcontroller
Author
van de Goor, Ad ; Gaydadjiev, Georgi ; Hamdioui, Said
Author_Institution
ComTex, Gouda, Netherlands
fYear
2010
fDate
8-12 March 2010
Firstpage
214
Lastpage
219
Abstract
Many systems are based on embedded microcontrollers. Applications demand for production and Power-On testing, including memory testing. Because low-end microcontrollers may not have memory BIST, the CPU will be the only resource to perform at least the Power-On tests. This paper shows the problems, solutions and limitations of CPU-based at-speed memory testing, illustrated with examples from the ATMEL RISC microcontroller.
Keywords
embedded systems; integrated circuit testing; memory architecture; microcontrollers; reduced instruction set computing; ATMEL RISC microcontroller; CPU; embedded microcontroller; low-end microcontroller; memory BIST; memory testing; power-on testing; Assembly; Built-in self-test; Computer architecture; Microcontrollers; Performance evaluation; Power engineering computing; Production; Reduced instruction set computing; Registers; System testing; ATMEL RISC microcontroller; CPU-based memory testing; Memory testing; assembler language;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4244-7054-9
Type
conf
DOI
10.1109/DATE.2010.5457210
Filename
5457210
Link To Document