Title :
Effects of S/D non-overlap and high-κ dielectrics on nano CMOS design
Author :
Chang, Sung-il ; Lee, Hyunjin ; Lee, Jongho ; Shin, Hyungcheol
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
Abstract :
A new MOSFET structure with non-overlap S/D to gate and high-ic spacer was proposed. Extensive simulation data and some measured data were reported. The proposed structure showed very good subthreshold slope, DIBL, GIDL compared to those of overlap structure. By controlling the non-overlap length, we could obtain reasonable speed and on-current characteristics. Also we have shown the GIDL depends on strongly the difference of the gate and the spacer dielectric constants. Based on the results, we conclude reasonable non-overlap length is between 0 (just meet the gate edge) to 10 mn
Keywords :
CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit design; integrated circuit modelling; nanotechnology; 0 to 10 nm; Al2O3-SiO2; DIBL; GIDL; MOSFET structure; Ta2O5-SiO2; drift diffusion model; nano CMOS; non-overlap S/D; short channel effect; simulation; spacer material; subthreshold slope; Acceleration; CMOS technology; Degradation; Design methodology; Dielectric materials; Electrons; High-K gate dielectrics; MOSFET circuits;
Conference_Titel :
Semiconductor Device Research Symposium, 2001 International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-7432-0
DOI :
10.1109/ISDRS.2001.984608
