Title :
A shear based optimization of adhesive thickness for die bonding
Author :
Hokanson, Karl E. ; Bar-Cohen, Avram
Author_Institution :
Dept. of Mech. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
In low-cost integrated circuit (IC) packaging, a thin layer of adhesive is often used to bond the die to a leadframe or substrate. Because of the poor thermal conductivity of the adhesive, a thick layer will result in elevated chip temperatures. However, due to the differential expansion between the silicon and metal, a thin layer will result in high shear stress, in the adhesive, and along the bonded surfaces. In this study, first order thermal and thermo-structural analytical relations for shear stress are used to determine the appropriate thickness of the adhesive layer between a die and a leadframe paddle, as encountered in PDIP packages. Numerical simulation, with finite element models, is used to examine the assumptions underpinning the analytical relations and to verify the analytical results. Using a filled-epoxy with an adhesion strength of 25 MPa, adhesive layer thicknesses between 0.027 and 0.2 mm are found to be suitable for this application. Assuming equal loss of reliability, due to chip temperature increases and shear stress increases, an optimum die-bond thickness of 0.16 mm is found. The finite element computations appear to support the assumption that elevated shear stress is the most likely cause of die-bond structural failure
Keywords :
adhesion; finite element analysis; microassembling; modelling; optimisation; packaging; simulation; thermal analysis; 0.027 to 0.2 mm; 0.16 mm; PDIP packages; adhesion strength; adhesive layer; adhesive thickness; bonded surfaces; die bonding; die-bond structural failure; filled-epoxy; finite element models; first order thermal analytical relations; integrated circuit packaging; leadframe; low-cost IC packaging; numerical simulation; optimum die-bond thickness; reliability; shear based optimization; shear stress; substrate; thermo-structural analytical relations; Adhesives; Bonding; Finite element methods; Integrated circuit packaging; Microassembly; Numerical simulation; Silicon; Temperature; Thermal conductivity; Thermal stresses;
Conference_Titel :
Thermal Phenomena in Electronic Systems, 1994. I-THERM IV. Concurrent Engineering and Thermal Phenomena., InterSociety Conference on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-1372-0
DOI :
10.1109/ITHERM.1994.342906