Title :
A multi-standard video decoder for high definition video applications
Author :
Chien, Cheng-An ; Chien, Chih-Da ; Chu, Jui-Chin ; Guo, Jiun-In ; Cheng, Ching-Hwa
Author_Institution :
Dept. of CSIE, Nat. Chung-Cheng Univ., Chiayi, Taiwan
Abstract :
Through reducing 70% of external memory bandwidth and 60% of computational complexity, the proposed 252 Kgates/71 mW/0.13 um multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder reduces 72% in gate count and 87% in power consumption as compared to the state-of-the-art design, when operating at 120 MHz for real-time HD1080 video decoding with single AHB-based SDR memory.
Keywords :
computational complexity; high definition video; video coding; AHB-based SDR memory; computational complexity; external memory bandwidth; frequency 120 MHz; high definition video applications; multistandard video decoder; Automatic voltage control; CMOS technology; Clocks; Costs; Decoding; Energy consumption; Hardware; High definition video; Random access memory; Testing;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118164
