DocumentCode
2260276
Title
Quadrature Direct Digital Frequency Synthesizer with High Compression Ratio
Author
Zhanfeng, Zhao ; Zhiquan, Zhou ; Xiaolin, Qiao
Author_Institution
Harbin Inst. of Technol., Harbin
fYear
2006
fDate
27-30 Nov. 2006
Firstpage
1
Lastpage
5
Abstract
This paper presents a new QDDFS architecture with high compression ratio, which based on the principles of non-linear approach and trigonometric approximation. The principles have been analyzed systemically and all the parameters have been optimized. A high compression ratio of 762 at 93.5 dBc in a 16 bit system. The architecture is realized by Quartus-II at maximum clock frequency of 100 MHz. In the end, a proposed architecture is given.
Keywords
approximation theory; clocks; data compression; direct digital synthesis; QDDFS architecture; frequency 100 MHz; high compression ratio; maximum clock frequency; nonlinear approach; quadrature direct digital frequency synthesizer; trigonometric approximation; Approximation methods; Clocks; Communication switching; Electronic mail; Frequency control; Frequency synthesizers; Read only memory; Signal generators; Signal to noise ratio; Table lookup; Non-Linear approach; QDDFS; Trigonometric approximation;
fLanguage
English
Publisher
ieee
Conference_Titel
Communication Technology, 2006. ICCT '06. International Conference on
Conference_Location
Guilin
Print_ISBN
1-4244-0800-8
Electronic_ISBN
1-4244-0801-6
Type
conf
DOI
10.1109/ICCT.2006.341728
Filename
4146292
Link To Document