Title :
A Class D amplifier output stage with low THD and high PSRR
Author :
Chun Kit Lam ; Meng Tong Tan
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
This paper presents a class D amplifier output stage with low total harmonic distortion (THD) and high power supply rejection ratio (PSRR). The class D output stage reduces the non-linearities and supply noise by means of a second-order negative feedback loop embodying a single stage second-order integrator and a Schmitt trigger comparator. Unlike conventional feedback, the reference input signal of the feedback loop is a digital pulse width modulated signal. The feedback loop compensates for any external errors or non-linearities in the output PWM signal by modulating the pulse width of the output signal. Based on simulation using AMS 0.35 mum CMOS process, our proposed closed-loop output stage can achieve a PSRR of .90 dB at 1 kHz and a THD well below 0.05% up to 10 kHz. This shows that negative feedback can effectively be employed to improve the PSRR and THD performance of a class D output stage with digital PWM input.
Keywords :
CMOS integrated circuits; amplifiers; harmonic distortion; integrating circuits; pulse width modulation; trigger circuits; AMS CMOS process; Schmitt trigger comparator; class D amplifier output stage; closed-loop output stage; digital pulse width modulated signal; frequency 1 kHz; high power supply rejection ratio; low total harmonic distortion; second-order negative feedback loop; single stage second-order integrator; size 0.35 mum; Feedback loop; High power amplifiers; Negative feedback loops; Noise reduction; Power supplies; Pulse width modulation; Pulsed power supplies; Space vector pulse width modulation; Total harmonic distortion; Trigger circuits;
Conference_Titel :
Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on
Conference_Location :
Taipei
Print_ISBN :
978-1-4244-3827-3
Electronic_ISBN :
978-1-4244-3828-0
DOI :
10.1109/ISCAS.2009.5118170