Design of a Silicon Carbide JFET based operational amplifier for gain and CMRR performance

Although silicon carbide (SiC) JFETs are superior candidates for high temperature and harsh environment applications, they exhibit significant design challenges even at room temperature, such as low intrinsic gain and low gate to source voltage range (GSVR) requirement. The primary goal of this paper is to present an opportunity demonstrating the feasibility of a fully SiC JFET based operational amplifier (opamp). Considering wide bandgap property of SiC material, the same design is not feasible using silicon JFETs. An opamp based on two types of enhancement and depletion mode SiC JFETs is designed, fabricated, and tested. Before designing the opamp, enhancement and depletion mode SiC JFETs are characterized and modeled for SPICE and simulation. In order to offset the low intrinsic gain effect of the transistors and achieve high overall gain and common mode rejection ratio (CMRR), gain enhancing design techniques such as cascoding and bootstrapping are applied in a way that low GSVR requirement is taken into account. The performance of the final opamp shows 67 dB of open loop gain and 73 dB of CMRR.