A semi-digital interface for capacitive sensors

A new technique and circuit topology is proposed to readout the output of a capacitive sensor for lab on chip (LOC) applications. Using time-mode signal processing and adopting modified digital blocks, a first-order delta-sigma interface is developed. It offers an incredibly compact and low-power solution where analog precision is achieved by making advantage of digital design. The design is capable of being tuned for different ranges of input capacitance as well as different resolutions where applicable. The proposed circuit is layout in 0.8-mum DALSA CMOS process. Post-layout simulation shows a capacitance change of 5 fF can be measured with error less than 2% in 500 mus. Also, the resolution of the circuit can be increased by 25 times to measure an input capacitance as small as 0.2 fF.