Title :
VLSI implementation of pulse coded winner take all networks
Author :
Hylander, Paul ; Meader, J. ; Frie, Eddie
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
A VLSI implementation of a pulse coded winner-take-all network is presented. The pulse coded winner-take-all network uses a single inhibition bus to implement lateral inhibition. One advantage of the pulse coded winner-take-all is that it has a wiring complexity of O(n). This is in contrast with the standard winner-take-all whose wiring complexity is of O(n2). The pulse coded version also has the advantage of preserving the relative magnitude of the winning neuron´s incoming signals. Experimental results are presented
Keywords :
CMOS integrated circuits; VLSI; cellular neural nets; computational complexity; neural chips; CMOS; VLSI implementation; incoming signals; lateral inhibition; pulse coded winner take all networks; relative magnitude; single inhibition bus; wiring complexity; Capacitors; Computer science; Lifting equipment; Neural networks; Neurons; Pulse circuits; Threshold voltage; Trigger circuits; Very large scale integration; Wiring;
Conference_Titel :
Circuits and Systems, 1993., Proceedings of the 36th Midwest Symposium on
Conference_Location :
Detroit, MI
Print_ISBN :
0-7803-1760-2
DOI :
10.1109/MWSCAS.1993.342936
