Clock gating and clock enable for FPGA power reduction

This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III and a 45 nm CMOS Spartan 6 FPGAs are presented. The selected circuits used as benchmarks are different type of multipliers. Results of power consumption in active and standby modes are presented and compared.