The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle

Author

Yang, Wei-Bin ; Kuo, Shu-Chang ; Chu, Yuan-Hua ; Cheng, Kuo-Hsing

Author_Institution

SoC Technol. Center, Ind. Technol. Res. Inst., Taiwan

Volume

3

fYear

2005

fDate

28 Aug.-2 Sept. 2005

Abstract

Because SOC (system-on-a-chip) needs multiple clocks and mostly with 50% duty cycle in same chip, in this paper, we propose a new approach of programmable pseudo fractional-N clock generator to reach a simple solution. We use multiphase outputs of voltage-controlled oscillator (VCO) in a phase-locked loop (PLL), to generate the needed frequencies with 50% duty cycle. Moreover, a control logic is also built in the structure to make multiple frequency outputs programmable. The circuits are processed in a standard 0.13μm CMOS technology, and work with a supply voltage of 1.2V.

Keywords

CMOS integrated circuits; clocks; logic circuits; phase locked loops; programmable circuits; system-on-chip; voltage-controlled oscillators; 0.13 micron; 1.2 V; CMOS technology; control logic; duty cycle; multiphase output; phase-locked loop; programmable pseudo fractional-N clock generator; system-on-chip; voltage-controlled oscillator; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Frequency; Phase locked loops; Programmable control; System-on-a-chip; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on

Print_ISBN

0-7803-9066-0

Type

conf

DOI

10.1109/ECCTD.2005.1523093

Filename

1523093