Background subtraction algorithm for moving object detection in FPGA

Currently, both the market and the academic communities have required applications based on image and video processing with several real-time constraints. On the other hand, detection of moving objects is a very important task in mobile robotics and surveillance applications. In order to achieve an alternative design that allows for rapid development of real time motion detection systems, this paper proposes a hardware architecture for motion detection based on the background subtraction algorithm, which is implemented on FPGAs (Field Programmable Gate Arrays). For achieving this, the following steps are executed: (a) a background image (in gray-level format) is stored in an external SRAM memory, (b) a low-pass filter is applied to both the stored and current images, (c) a subtraction operation between both images is obtained, and (d) a morphological filter is applied over the resulting image. Afterward, the gravity center of the object is calculated and sent to a PC (via RS-232 interface). Both the practical results of the motion detection system and synthesis results have demonstrated the feasibility of FPGAs for implementing the proposed algorithms on an FPGA based hardware platform. The implemented system provides one processed pixel per FPGA´s clock cycle (after the latency time) and speed-ups the software implementation (using the real-time xPC Target OS from MathWorks) by a factor of 32.