Design of an 8192-bit RSA cryptoprocessor based on systolic architecture

This paper presents the design of an 8192-bit RSA cryptoprocessor using a radix 2 Montgomery multiplier based on a systolic architecture. In this case, the Montgomery multiplier simultaneously performs two multiplications, and the cryptoprocessor carries out the modular exponentiation using the binary exponentiation algorithm. The designs are described using generic structural VHDL and synthesized on the EP3SL150F1152C2, using Quartus II 11. The hardware synthesis and performance results show that the designed cryptoprocessor presents a good area-throughput trade-off and it can be used as a suitable core for an RSA cryptosystem embedded into a SoC.