Invited Talk

Because of trends in scaling, in the near future every high performance dice will contain a massive number of defects and process aggravated noise and performance problems. In an attempt to obtain useful yields, designers and test engineers will need to adopt a qualitatively different approach to their work. They will need to learn, enhance and deploy techniques such as fault- and defect-tolerance. For some applications, they may even apply error-tolerance, a somewhat controversial emerging paradigm. A circuit is error-tolerant (ET) with respect to an application, if (1) it contains defects that cause internal and may cause external errors, and (2) the system that incorporates this circuit produces acceptable results. In this presentation we illustrate and give quantitative bounds on several factors that will shape the future of digital design. We compare and contrast defect and fault-tolerant schemes with that of error-tolerance. We discuss how yield can be optimized by appropriately selecting the granularity of spares in light of defect densities and interconnect complexity. We show that several large classes of consumer electronic applications are resilient to errors, and how error-tolerance can then be used to significantly enhance effective yield. Finally, we discuss and illustrate several test issues related to error-tolerance.