An MPEG-4 AAC decoder FPGA implementation for the Brazilian digital television

Author

Renner, Adriano ; Susin, Altamiro Amadeu

Author_Institution

PPGEE, UFRGS, Porto Alegre, Brazil

fYear

2012

fDate

20-23 March 2012

Firstpage

1

Lastpage

6

Abstract

This paper presents an MPEG-4 AAC decoder described in VHDL language and compliant with the Brazilian Digital Television standard (SBTVD). It has been synthesized to an Altera Cyclone II 2C35 FPGA using 26549 logic elements and 248704 memory bits. The implemented architecture has been verified using an Altera DE2 prototyping board, being capable of decoding stereo signals coded as MPEG-4 AAC Low Complexity audio objects. The minimum operating frequency required for real time decoding of a stereo audio stream with a sampling rate of 48 kHz is 4 MHz and the implemented decoder is capable of running at 56 MHz, meeting the requirements. This decoder design is intended to be integrated with a system on chip for the SBTVD set-top box.

Keywords

audio coding; audio streaming; computational complexity; digital television; field programmable gate arrays; hardware description languages; logic design; system-on-chip; 248704 memory bits; 26549 logic elements; Altera Cyclone II 2C35 FPGA; Altera DE2 prototyping board; Brazilian digital television standard; MPEG-4 AAC decoder FPGA implementation; MPEG-4 AAC low complexity audio objects; SBTVD set-top box; VHDL language; decoder design; frequency 4 MHz; frequency 48 kHz; frequency 56 MHz; minimum operating frequency; sampling rate; stereo audio stream; stereo signals decoding; storage capacity 248704 bit; system on chip; Audio coding; Decoding; Filter banks; Quantization; Standards; Transform coding; Transforms; AAC LC; Audio Decoder; MPEG-4 AAC; SBTVD;

fLanguage

English

Publisher

ieee

Conference_Titel

Programmable Logic (SPL), 2012 VIII Southern Conference on

Conference_Location

Bento Goncalves

Print_ISBN

978-1-4673-0184-8

Type

conf

DOI

10.1109/SPL.2012.6211796

Filename

6211796