DocumentCode
2260923
Title
B-spline generation in FPGA
Author
Silva, Luiz Marcelo Chiesse da ; De Paiva, Maria Stela Veludo
Author_Institution
Electr. Eng. Dept., Fed. Univ. of Technol. - Parana, Paraná, Brazil
fYear
2012
fDate
20-23 March 2012
Firstpage
1
Lastpage
5
Abstract
B-spline curves can represent almost any smooth shape, being adopted by file exchange standards, used as a wavelet basis for multiresolution systems and manufacturing efficiency is increased using b-splines toolpaths. The respective algorithms for conventional CPUs demand great computational effort, requiring another hardware architectures, like GPUs, for better processing efficiency. This paper describes a system on a chip that generates b-splines curves from given control points in a concurrent way, based in a FPGA platform, including features that are not addressed by the few works in the area. This system is faster than a quadcore CPU in the order of the number of generated points, at the same clock rate. The independence of the number of generated and initial control points, and the processing determined by the FPGA capacity, makes it a better choice for embedded systems in relation to conventional CPUs.
Keywords
computational geometry; embedded systems; field programmable gate arrays; splines (mathematics); system-on-chip; wavelet transforms; FPGA platform; b-spline curve generation; b-splines toolpaths; embedded systems; file exchange standards; manufacturing efficiency; multiresolution systems; quadcore CPU; system on a chip; wavelet basis; Field programmable gate arrays; Graphics processing unit; Spline; Surface reconstruction; Surface treatment; Three dimensional displays; FPGA; b-spline; curves; reconfigurable logic; surface;
fLanguage
English
Publisher
ieee
Conference_Titel
Programmable Logic (SPL), 2012 VIII Southern Conference on
Conference_Location
Bento Goncalves
Print_ISBN
978-1-4673-0184-8
Type
conf
DOI
10.1109/SPL.2012.6211798
Filename
6211798
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