Title :
Power and delay optimization for network on chip
Author :
Nickray, Mohsen ; Dehyadgari, Masood ; Afzali-Kusha, Ali
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
fDate :
28 Aug.-2 Sept. 2005
Abstract :
In this paper, we introduce an algorithm based on genetic algorithm for optimizing power consumption and delay of applications which are mapped on fat tree topology. We develop a NOC communication power model to estimate tire power consumption in communication. Our algorithm consists of Vertex mapping to PEs, Node mapping and Delay optimization. These steps map task graphs into a fat-tree NOC how had been minimum power consumption. Experimental results show that we could achieve the efficiency of 94%.
Keywords :
delay circuits; genetic algorithms; network topology; network-on-chip; power consumption; trees (mathematics); NOC communication power model; Vertex mapping; delay optimization; fat tree topology; genetic algorithm; low power; network on chip; power consumption; Clocks; Communication switching; Delay; Energy consumption; Genetic algorithms; Network topology; Network-on-a-chip; Routing; Switches; Tree graphs;
Conference_Titel :
Circuit Theory and Design, 2005. Proceedings of the 2005 European Conference on
Print_ISBN :
0-7803-9066-0
DOI :
10.1109/ECCTD.2005.1523113
